Since the time of development of a memory cell of a dynamic random access memory made up of a sole transistor and a sole capacitor, it has become difficult to simplify the structure and to save the areal space by circuit configuration. Thus, attempts have been made to realize saving in areal space by a three-dimensional capacitor structure by the device process, self-alignment of contact interconnections and by multi-layered interconnections. In these attempts, the memory cell structure, starting from a planar capacitor structure in which a gate electrode 505 of a MOS transistor and a counterelectrode 509 of a capacitor charge holding electrode are formed on a semiconductor substrate 501, as shown in FIG. 48, was roughly diverged into a trench capacitor structure and a stacked structure. In the trench capacitor structure, shown in FIG. 49, a hole or a trench 604 is formed in a semiconductor substrate 601, carrying a gate electrode 605 of a MOS transistor and a counterelectrode 603 of a capacitor charge holding electrode, and the hole surface is used as a capacitor charge holding electrode, that is as a capacitance forming diffusion layer 607. In the stacked structure, shown in FIG. 50, a capacitor charge holding electrode 711, that is a stacked electrode 711, is formed on a semiconductor substrate 701, carrying a gate electrode 705 of a MOS transistor and a counterelectrode 709 of the capacitor charge holding electrode.
Referring to FIG. 48, 502 is a device isolating oxide film, 503 an active area, 506 a gate oxide film, 507 is a capacitance forming diffusion layer, 508 a bit line connecting diffusion layer, 510 a capacitance insulating film, 513 a bit line and 515 is a connection hole. Referring to FIG. 49, 602 is a device isolating oxide film, 606 a gate oxide film, 608 a bit line connection diffusion layer, 609 a counterelectrode of a charge holding electrode, 610 a capacitance insulating film, 613 a bit line and 615 is a connection hole. Referring to FIG. 50, 703 is an active area, 705 a gate electrode, 706 a gate oxide film, 707 a capacitance forming diffusion layer, 708 a bit line connection diffusion layer, 710 a capacitance insulating film, 713 a bit line, and each of 714, 715 is a connection hole.
The trench capacitor structure was further diverged into a system having a substrate as a capacitor charge holding electrode, as shown in FIG. 49, and a system having a substrate 801 as a counterelectrode of a capacitor charge holding electrode, as shown in FIG. 51. Referring to FIG. 51, 802 is a device isolating oxide film, 803 an active area, 804 a trench, 805 a gate electrode, 806 a gate oxide film, 807 a capacitance forming diffusion layer, 808 a bit line connection diffusion layer, 809 a charge holding electrode, 810 a capacitance insulating layer, 813 a bit line, and 815 is a connection hole.
Referring to FIG. 50, the stacked structure was evolved from the on-word-line stacked electrode system of forming a stacked electrode 711 on a gate electrode 705 to a on-bit-line stacked electrode structure, as shown in FIG. 52, of forming a capacitor made up of a stacked electrode 911 and a counterelectrode 909 of the charge holding electrode.
The following problems have been encountered and/or turned out in the course of investigations toward the present invention.
Recently, with the increasing system speed, a demand for raising the data transfer speed between a logic device such as a micro-processor or a gate array and the memory device is increasing. For raising the data transfer speed between chips, a dedicated input/output circuitry and dedicated boards are required. In addition, power consumption at the input/output circuitry and the package cost are increased, such that it has become necessary to have the logic device and the memory device mounted on a sole chip.
In contradistinction from the manufacturing process for a logic device for which basically the manufacturing process for the CMOS transistor suffices, the manufacturing process for a memory device is in need of a manufacturing process for a three-dimensional capacitor in addition to the manufacturing process for a CMOS transistor.
Therefore, since the manufacturing process for the three-dimensional capacitor represents a redundant process for the area of the logic device, the cost of a sole chip is higher than that of a chip of the logic device by itself and a sole chip of the dynamic random access memory device.
Moreover, in the memory cell of the stacked structure, since a capacitor made up of the stack electrode 711, 911 and the counterelectrode 709, 909 of the charge holding electrode after formation of the gate electrode of the MOS transistor as shown in FIGS. 50 and 52, the extent/amount of the heat treatments after formation of the MOS transistor is increased to deteriorate characteristics of the MOS transistors.
In the trench capacitor structure, since the capacitor structure is produced before formation of the gate electrode, the problem of deterioration of MOS transistor characteristics is not liable to be raised. However, the electrode for the capacitor and the capacitance insulating film are formed by a process other than the logic device process, thus inevitably increasing the number of steps and cost.
For overcoming these problems, a proposal has been made for systems for manufacturing the dynamic random access memory device by the manufacturing process for the CMOS transistor by using an insulating film for the capacitor and an insulating film for the transistor in common and by using an electrode for a capacitor and an electrode for the transistor in common (see a reference material `ISSCC96 FP16.1`). In one of these systems, since the capacitor is of a planar structure, the memory cell area is excessively increased. In another of the above systems, similarly employing the capacitor electrode and the transistor electrode in common, a trench capacitor structure is used, in which a trench is formed in a capacitor forming region of the substrate prior to formation of the insulating film for the transistor, with the hole surface being used as a capacitor charge holding electrode (see JP Patent Kokai Publication JP-A-1-231363).